2 input AND gate, 74AHC1G08QC5G Replace 74AHC1G08GW
74AHC1G08Q 74AHC1G08Q.pdf
FEATURES

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PIN CONFIGUTION
CROSS
74AHC1G08-Q100 74AHC1G08-Q100.pdf

No.13681

FEATURES

• Automotive product qualification 

  in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to 

  +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 2.0 to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• CMOS low power dissipation

• Latch-up performance exceeds 

  100 mA per JESD 78 Class II Level A

• Symmetrical output impedance

• Balanced propagation delays

• Input levels:

• For 74AHC1G08-Q100: CMOS level

• For 74AHCT1G08-Q100: TTL level

• ESD protection:

• MIL-STD-883, method 3015 exceeds 2000 V

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A 

  exceeds 200 V (C = 200 pF, R = 0 Ω)

PIN CONFIGUTION
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