Quad 2 input NAND gate,74LVC00AXTS14G Replace 74LVC00APW
74LVC00AXTS14G 74LVC00AXTS14G.pdf
FEATURES

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PIN CONFIGUTION
CROSS
74LVC00APW 74LVC00APW.pdf

No.13710

FEATURES

 Overvoltage tolerant inputs to 5.5 V

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Multiple package options

 Specified from -40 °C to +85 °C and -40 °C to +125 °C

PIN CONFIGUTION
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